SoC Team | RTL Design Lead

Lead a team of RTL engineers responsible for complete RTL implementation of all SoC blocks for the flight controller chip. Define micro-architecture from specification, direct block ownership, and guarantee RTL quality across design correctness, synthesis, timing closure, and DFT readiness. 

• Lead micro-architecture definition from architecture specification: translate spec documents into block-level micro-architecture specs for RTL engineers.
• Implement and review synthesizable SystemVerilog RTL for CPU subsystems, AMBA bus fabric, and flight controller peripheral IPs.
• Design and review FSM (Finite State Machine) logic, datapath pipelines, and arithmetic units ensuring correctness and timing closure.
• Enforce RTL coding guidelines: naming conventions, synchronous reset strategy, CDC/RDC rules, and synthesis-friendly coding style.
• Drive RTL-to-synthesis handoff: CDC/RDC lint sign-off, clock tree constraints, UPF power intent, coverage closure.
• Own DFT strategy: scan chain insertion, MBIST, boundary scan — coordinate with Physical Design and Test Engineering teams.
• Support Physical Design with SDC constraints, scan chain reordering, and ECO implementation during timing closure.
• Lead implementation of flight controller IPs: CAN-FD controller, motor-control PWM timers, IMU (SPI/I2C) interface blocks.
• Review and approve micro-architecture specs; ensure full traceability to top-level SoC architecture specification. 

• Bachelor’s or Master’s in Electrical/Computer Engineering.
• 7+ years RTL design experience; 3+ years as team lead or senior RTL architect on commercial SoC tape-outs.
• Expert SystemVerilog — synthesizable RTL coding, FSM design, datapath/pipeline implementation.
• Strong experience coding RTL from specification: reading architecture specs and producing correct, clean micro-architecture.
• Deep knowledge of Arm Cortex-M/R, AMBA AXI/AHB/APB bus protocols, and on-chip memory subsystems.
• Hands-on EDA: Synopsys DC/Fusion Compiler or Cadence Genus for synthesis; VCS or Xcelium for simulation.
• Experience with UPF power intent and multi-voltage/power-gated designs.
• Solid DFT: scan insertion, ATPG, MBIST, boundary scan flows.
• Good English and Vietnamese skills. 

Nice to Have: 

• Experience implementing CAN-FD, motor-control PWM, or real-time peripherals for UAV/drone applications.
• Familiarity with PX4/ArduPilot and flight controller hardware bring-up.
• RISC-V custom IP or open-source core integration experience. 

Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:

• Competitive compensation package, aligned with capabilities and performance.
• Project bonuses when you join ODC (Offshore Development Center) projects
• Comprehensive benefits and welfare package (FPT Care, annual company trips, team building activities, annual health check-ups) in line with a large-scale corporation.
• Exposure to a diverse ecosystem across the semiconductor value chain, including PMIC, IP Solutions, Engineering Services, ATE & Packaging, Camera & Drone, and IoT Devices.
• Access to professional training and development programs within FPT Corporation.
• Working hours: 9:00 AM – 6:00 PM, Monday to Friday.