Thực hiện quy trình thiết kế vật lý end-to-end cho chip tiên tiến (7nm, 5nm, 3nm).
Yêu cầu
1.5-3.5 năm kinh nghiệm ngành
STA (Primetime), SI/Crosstalk, IR drop & EM analysis
Thiết kế low-power: multi-Vt, multi-voltage (UPF), power/clock gating
Physical verification & signoff
Làm việc node tiên tiến 7nm/5nm/3nm
Trách nhiệm
Floorplanning, power planning, placement, CTS, routing
Post-route optimization và timing closure mọi mode/corner
Khắc phục DRC, LVS, ERC, signoff violations
Áp dụng kỹ thuật low-power: multi-Vt, multi-voltage (UPF), power/clock gating
Có thì tốt
Tự động hóa methodology (scripts/flows)
Hợp tác chặt chẽ RTL, DFT, Foundry, CAD
Tóm tắt bằng AI từ JD gốc, đọc JD gốc trước khi ứng tuyển.
Job Summary
Perform end‑to‑end physical design flow: Floorplanning Power planning (PG grid, IR) Placement & optimization CTS (Clock Tree Synthesis) Routing
Key Responsibilities
Post‑route optimization Achieve timing closure across all modes and corners Resolve DRC, LVS, ERC and signoff violations Handle low‑power design techniques: Multi‑Vt, Multi‑voltage (UPF) Power gating, clock gating Perform physical verification and signoff:
Skill Requirements
STA (Primetime) SI / Crosstalk IR drop & EM analysis Work on advanced nodes (7nm, 5nm, 3nm or below) Collaborate with: RTL & Micro‑architecture teams
Other Requirements
DFT & Test engineers Foundry and CAD teams Debug complex timing, congestion, power, and variability issues Drive methodology improvements and automation (scripts/flows)
