Alternate Job Titles
- Physical Design Lead
- ASIC Physical Design Manager
- Backend Design Manager
- Place and Route Manager
- Physical Implementation Manager
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent a decade in physical design, and you know that the difference between a chip that tapes out clean and one that burns months in respins is usually a decision made during floorplanning that nobody questioned hard enough. You are the person who questions it. You have closed timing on designs running north of 2 GHz, and you understand that at those frequencies, every picosecond matters and every SI issue that looks small in simulation becomes a showstopper in silicon.
Managing a team is not about delegation for you. It is about building engineers who can see three steps ahead, who understand why a clock tree decision today affects yield six months from now. You are comfortable in the gap between what the spec says and what will actually work. When a design review surfaces a conflict between performance targets and physical constraints, you pull the right people together, sketch the tradeoffs, and drive to a decision the team can execute against.
You know the Synopsys toolchain deeply because you have lived in it. ICC2, Fusion Compiler, PrimeTime, these are instruments you have tuned to deliver results on 7nm, 5nm, and 3nm nodes where the margin for error is measured in atoms. At Synopsys, you will lead physical design for the interconnect technology that makes AI infrastructure possible.
What You'll Be Doing
- Lead the complete physical design flow for high-speed die-to-die interconnect chips operating at 2 GHz and above, from RTL handoff through tape-out
- Drive floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification on advanced nodes including 7nm, 5nm, and 3nm
- Own timing closure across all corners and modes, working with front-end teams to resolve critical paths and ensure SI/PI integrity
- Build, manage, and mentor a global physical design team, setting technical direction and developing engineers at multiple levels
- Collaborate with architecture, design, verification, and package teams to align physical implementation with product requirements and manage milestones
- Champion automation and methodology improvements using Tcl, Python, and Perl scripts that increase team productivity and design quality
